TestScript AI
Studio

Fault Model Engine

// ATPG · COMPARABLE TO TESSENT

Select from 6 industry-standard fault models, configure coverage targets and process nodes (3nm–180nm), enable EDT-style pattern compression, and run ATPG in one click. Per-model coverage gauges, vector counts, and ATPG timing are displayed in a live dashboard. AI Fault Analysis (Ollama-powered) identifies coverage gaps and DPM reduction estimates. Exports full Verilog testbench with fault-specific test vectors.

Waveform Viewer

// VCD · COMPARABLE TO SIMVISION

Parses standard VCD files produced by Verilator or Icarus Verilog and renders a scrollable, zoomable timing diagram. Signal name column with bit-width display, colour-coded 1-bit and multi-bit bus waveforms, hex value labels, and a drag cursor for time-point inspection. AI waveform analysis (Ollama-powered) identifies timing violations, glitches, and coverage gaps.

DFT Checklist & Scan Planner

// SCAN · MBIST · JTAG · IJTAG

20 structured DFT readiness checklist items across 6 categories — each with IEEE/industry reference, status picker (Not Started / In Progress / Done / N/A), engineer notes, and on-demand AI guidance from Ollama. Generates a synthesisable Verilog scan chain wrapper with MBIST, JTAG TAP, and power-aware DFT ports.

ATE Export

// STIL · WGL · SVF · CSV

Export test patterns in ATE-ready formats: STIL (IEEE 1450) for Advantest T2000/Teradyne UltraFLEX, WGL for Agilent 93000/Cadence ETS, SVF for JTAG/OpenOCD, and CSV for any ATE. Full timing configuration, scan chain procedures, fault model selection, and AI compatibility check included.

Silicon Lifecycle & Reliability

// WEIBULL · ARRHENIUS · HTOL · NBTI

Weibull failure analysis (β shape factor, η characteristic life), Arrhenius acceleration factor and projected field lifetime estimation. Logs HTOL, NBTI, HCI, Electromigration, TDDB, and ESD reliability test runs with session-persistent trend charts per failure mechanism. AI reliability risk summary via Ollama. Comparable to Siemens Solido Variation Designer and PDF Solutions Exensio.

Power-Aware Test Planner

// UPF · CPF · DVFS · ISO CELLS

Multi-Vdd power domain visual map, isolation cell checker (flags missing/incorrect ISO cells), power-gating test sequence generator, DVFS (Dynamic Voltage-Frequency Scaling) corner sweep planner, and UPF/CPF power intent Verilog stub generator. AI power risk analysis identifies missing isolation and retention requirements. Comparable to Cadence Genus Power and Synopsys PrimePower.

Coverage Metrics Engine

// TOGGLE · FSM · BRANCH · EXPRESSION

Track toggle, branch, condition, expression, FSM state, and FSM arc coverage in a unified dashboard. Visual heat-map overlay on Verilog source lines highlights uncovered paths. Parses Verilator .dat/.info coverage output natively (offline-first). Manual entry for session-persistent run logging. AI coverage gap analysis via Ollama identifies critical untested paths and suggests stimuli. Comparable to Cadence IMC and Siemens Questa Coverage.

Constraint-Random Test Generator

// CRT · SEEDED RNG · VERILOG-2005

Define value ranges, sequences, forbidden states, and distribution ratios as constraint sets. AI-guided constraint refinement (Ollama) improves stimulus quality for hard-to-reach corner cases. Seeded, reproducible random vector generation engine ensures regression test repeatability. Outputs standard Verilog-2005 testbench with named initial blocks. Session-persistent constraint sets. Comparable to Cadence JasperGold CRT and Synopsys VCS.

ESD Test Sequence Generator

// HBM · CDM · IEC 61000-4-2 · AEC-Q100

EGK's ESD coating specialisation (EGKAlphaT, DiamondHard, six proprietary formulations targeting 10⁵–10⁸Ω) directly informs this module. HBM/CDM/MM waveform templates per JEDEC JS-001, IEC 61000-4-2, and AEC-Q100. Full pin-to-pin stress sequence builder generates all-pin combination matrices automatically. Failure mode classification covers latch-up, oxide breakdown, junction damage, and metal damage. Exports Verilog-2005 stimulus and ATE-ready test vectors. AI failure risk analysis via Ollama.

Bus Protocol Test Generator

// SPI · I²C · UART · AXI4-Lite · APB

Generates correct-transaction templates plus corner-case and stress sequences for five industry-standard bus protocols. Configurable signal widths, clock dividers, and address maps. All output uses standard Verilog-2005 testbench stimulus — no SystemVerilog required. AI sequence review and corner-case suggestion via Ollama. Session-persistent protocol configurations. Comparable to Synopsys VC Verification IP and Cadence VIP Suite.

Timing Analysis Assistant

// SETUP · HOLD · SKEW · SLACK · SDC

Paste or import SDF annotation or timing-report text. Automatically parses setup violations, hold violations, clock skew, and slack into a structured violation table (path name, slack, type, start/end pin). Suggests SDC clock constraint fixes per violation. AI explains each violation in plain English via Ollama — making critical path issues accessible to junior engineers. No STA engine required; offline analysis and annotation only. Comparable to Synopsys PrimeTime and Cadence Tempus report parsing.

Memory BIST Pattern Deep-Dive

// MARCH-C · MATS+ · GALLOPING COL · WALK

Eight memory BIST algorithms — MARCH-C (gold standard, 11N operations, complete AF/SAF/TF/CF coverage), MATS+ (fast production, 5N), MARCH-X (6N, SAF+CF), MARCH-SS (22N, linked faults), Galloping Columns (address-decoder specialist), Walking-1/0, and Checkerboard. Configurable address and data width. Generates complete Verilog-2005 testbench per algorithm. Algorithm comparison table shows fault coverage vs test time trade-off. AI fault analysis and algorithm recommendation via Ollama. Comparable to Synopsys STAR Memory System and Mentor Tessent MBIST.